Thus it is often referred to as statistical multiplexing. The first part of the paper is devoted to a functional explanation of the various concepts referenced above. The balance of the paper is concerned with applications and systems-design considerations involving multiplexing and concentration techniques. The application section focuses on important economic factors pertaining to the selection and use of the various methods.
The role of line-sharing devices in contemporary common-carrier and end-user networks is also considered. The economic and technical aspects of these contrasting application environments are emphasized and illustrate the multiplicity of uses for line-sharing devices.
The concluding portion of the paper includes a discussion of system-design considerations. This section illustrates precisely how the decision to use multiplexers or concentrators in a typical computer-communication network is implemented. Various techniques for geographically positioning multiplexers and concentrators to minimize total costs are presented. The use of one of these procedures is demonstrated using a typical design problem as a case study.
Article :. Date of Publication: Nov. T H represents a small, fixed time interval for internal "housekeeping" functions. It should be noted that if the sum of the aggregate input signal frequencies falls below the aggregate maximum, through either reduction of any or all of the input frequencies F 1 through F N , or through a change by one or more of the input channel characteristics to a burst mode On, Off, On, Off, etc.
Because of variations in the number of data bits in the data fields DF n , the number of bits in the sub-fields SF n , which sub-fields SF n are the decremented bit counts of the actual number of data bits in the associated data fields DF n and which must be of a fixed length, i.
Note that the SF n bit count dedicated shall be the minimum binary word length which will contain the maximum input data word length count less the minimum input data word length count. As stated above, the input data bits of the input data signals on each of the input channels 1, 2, 3, 4 are coupled in parallel to separate, similar, associated concentrators 12, 13, 14, 15, respectively, each concentrator having similar half sections A and B; e.
All of the separate input data signal streams are coupled to the associated concentrators 12, 13, 14, 15 and are by an internal steering gate, coupled internally to the associated sections A1, A2, A3, A4 over a first sample time 1T S during which sample time the input data bits are counted and stored therein for forming a data field DF n from which a sub-field SF n is computed and stored. The computed sub-field SF n is a binary coded number representing the difference between the actual number of received input data bits that make up the data field DF n and the minimum number of input data bits expected to be received during a sample time T S.
This minimum number of input data bits expected to be received during any sample time T S may be of any number between 0 and a maximum number of input data bits equal to F n max T S but typically might be expected to be in the order of eight-tenths that of the maximum number of input data bits. At time t 1 the sample time 1T S is terminated and the steering gate, over the next successive or second sample time 2T S from t 1 to t 2 , gates the input data bits into the associated sections B1, B2, B3, B4.
Immediately after the termination of the first sample time 1T S , as at time t 1 , there is provided a short housekeeping time T H during which time the sub-field SF n is computed and the necessary decoding and enabling of the gates and circuitry of the concentrators are performed prior to retransmitting the sub-fields SF n and the data fields DF n stored in the respective sections A1, A2, A3, A4.
After this short delay time T H , controller 16 selectively enables the clocking signals of the transmitting frequency F 0 at the concentrators 12, 13, 14, 15 to successively retransmit the fixed length sub-fields SF 1 , SF 2 , SF 3 , SF 4 on the single output channel 20 after which time the variable length data fields DF 1 , DF 2 , DF 3 , DF 4 , the lengths of which are specified by the respective bit counts in the respectively associated sub-fields SF 1 , SF 2 , SF 3 , SF 4 , are then coupled to the single output channel 20 in the format previously discussed with particular reference to FIG.
This retransmission of the data fields DF n and their respective bit count sub-fields SF n occurs as a maximum duration over the sample time T S less the housekeeping time T H as from t 1 to t 2. However, because of the selection of the transmission frequency F 0 being greater than the sum of the individual average frequencies over any interval T S of the input data bit streams that are received on the input channels 1, 2, 3, 4, the actual transmit time T T is always less than the sample time T S.
As an example, using the values given in Table A the total actual number of data field bits transmitted is while the total number of sub-field bits is 35 providing a total of bits.
In this situation a simple time division multiplexing scheme would require an output channel capacity of greater than the one specified in the example presented with particular reference to Table A. As previously stated with respect to FIG. During this second sample time the input data bits are counted and stored therein for forming a data field DF n from which a sub-field SF n is computed and stored during the next following housekeeping time T H.
Further, during this next successive or second sample time 2T S , between the time t 1 to t 2 , the successive sub-fields SF 1 , SF 2 , SF 3 , SF 4 and the successive data fields DF 1 , DF 2 , DF 3 , DF 4 stored in the sections A1, A2, A3, A4, respectively, during the immediately previous first sample time 1T S during the time t 0 to t 1 , are, after the housekeeping time T H , successively coupled to the single output channel for retransmission at the output frequency F 0 in the manner as previously discussed with particular reference to FIGS.
During the next successive sample times T S , as at times t 2 to t 3 , t 3 to t 4 , t 4 to t 5 , etc. Thus, while the input data signals are being sampled in the sections A1, A2, A3, A4, the sampled portions of the input data signals previously stored in the sections B1, B2, B3, B4 are being retransmitted from sections B1, B2, B3, B4 and during the next successive sample time the input data signals being sampled in sections B1, B2, B3, B4 and the sampled portions of the input data signals previously stored in sections A1, A2, A3, A4 are being retransmitted from sections A1, A2, A3, A4.
The resulting output signal is of an output frequency F 0 on the single output channel and consists of the serial transmission of the output data words of FIG. As stated above, concentrator 12 consists of two similar half sections A1 and B1 and a steering gate 50 which during successive sample times T S successively couples the input data bits that make up the input data signal on input channel 1 to sections A1, B1, A1, B1, etc.
Using FIG. Starting at time t 0 , steering gate 50 is, via line 52, effected by an enable signal 54 from controller 16 which steers the received input data bits on input channel 1 into section A1 of concentrator By means of data cables 56A and 58A the input data bits are then fed into shift register 60A and all data bits are counted in bit counter 62A, respectively. In shift register 60A, the data bits of the data field DF 1 are shifted bit serially from the left to the right over the sample time 1T S , the number of data bits received establishing the right-most bit position of the data bits as stored in shift register 60A.
At time t 1 , gate 64A is enabled by controller The final bit count then held in counter 62A is entered, in parallel, into sub-field generator 66A, decoder 68A and counter 70A. In sub-field generator 66A, which includes a subtractor and shift register, the final bit count is decremented by the length of the minimum input data word expected using decrement quantity register 72A.
Sub-field generator 66A, from the decremented final bit count after the time represented by the housekeeping signal 74 then contains the binary coded bits that define sub-field SF 1. During the time represented by housekeeping signal 74, decoder 68A decodes the bit count and enables the one shift register 60A output gate 75A on the first input line 76A, the second input line 77A being coupled to the stage of shift register 60A in which the first received or right-most data bit of the data field DF 1 is stored.
After the completion of the decoding of the bit count by decoder 68A during housekeeping signal 74, an enable signal 80 from controller 16 is coupled to line 82A of sub-field gate 84A whereby the bits of sub-field SF 1 are serially coupled to line 86A and thence to the single output channel 20 via output data bus 18 at the frequency F 0. As indicated in FIG. Upon termination of enable signal 80c, an enable signal 88 from controller 16 is coupled to data field gate 90A by means of line 92A.
Gate 90A triggers counter 70A to count down from the bit count held therein triggering shift register 60A via line 94A to serially couple bits of the data field DF 1 to output channel 20 via line 96A and output data bus 18 at the frequency F 0 , all data bits passing serially through the one enabled shift register output gate 75A enabled by decoder 68A.
When counter 70A counts down to 0 it generates an enable signal 88a that via line 98A disables the shift register output gates A. Enable signal 88a, via line A, is also coupled to the next successive concentrator Enable signal 88a at a like positioned gate 90A in section A2 of concentrator 13 performs a similar function therein serially coupling the data field DF 2 onto the output data bus The successive coupling of the data fields DF 2 , DF 3 , DF 4 occur in the sections A2, A3, A4 of concentrators 13, 14, 15, respectively, under control of the enabling signals 88a , 88b, 88c.
Starting at time t 1 , steering gate 50 is, via line 52, effected by an enable signal from controller 16 which steers the received input data bits on input channel 1 into section B1 of concentrator By means of data cables 56B and 58B the input data bits are then fed into shift register 60B and all data bits are counted in bit counter 62B, respectively.
In shift register 60B, the data bits of the data field DF 1 are shifted bit serially from the left to the right over the sample time 2T S , the number of data bits received establishing the right-most bit position of the data bits as stored in shift register 60B. At time t 2 , gate 64B is enabled by controller The final bit count then held in counter 62B is entered, in parallel, into sub-field generator 66B, decoder 68B and counter 70B.
In sub-field generator 66B the final bit count is decremented by the length of the minimum input data word expected using decrement quantity register 72B. Sub-field generator 66B, from the decremented final bit count after the time represented by the housekeeping signal then contains the binary coded bits that define sub-field SF 1. During the time represented by housekeeping signal , decoder 68B decodes the bit count and enables the one shift register 60B output gate 75B on the first input line 76B, the second input line 77B being coupled to the stage of shift register 60B in which the first received or right-most data bit of the data field DF 1 is stored.
After the completion of the decoding of the bit count by decoder 68B during housekeeping signal , an enable signal from controller 16 is coupled to line 82B of sub-field gate 84B whereby the bits of sub-field SF 1 are serially coupled to line 86B and thence to the single output channel 20 via output data bus 18 at the frequency F 0. Upon the termination of enable signal c, an enable signal from controller 16 is coupled to data field gate 90B by means of line 92B.
Gate 90B triggers counter 70B to count down from the bit count held therein triggering shift register 60B, via line 94B, to serially couple bits of the data field DF 1 to output channel 20 via line 96B and output data bus 18 at the frequency F 0 , all data bits passing serially through the one enabled shift register output gate 75B enabled by decoder 68B.
When counter 70B counts down to 0 it generates an enable signal a that via line 98B disables the shift register output gates B. Enable signal a, via line B, is also coupled to the next successive concentrator
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